Multiple Successful Tapeouts on Samsung’s 3nm GAA Technology Validate Product Readiness of Synopsys Design Streams

Article by: Synopsys Inc.

To drive the adoption of Samsung’s 3nm gate-all-around (GAA) technology for designs requiring optimal power, performance, and surface area (PPA), Synopsys Inc.’s longstanding collaboration with Samsung Foundry has produced multiple successful test chip tapeouts on Synopsys digital and custom design tools and workflows, certified for Samsung Foundry’s most advanced process.

Common customers using Samsung Foundry’s SF3 technology can experience about 50% reduced power, 30% improved performance and 30% smaller area than the technology node demonstrated compared to SF5E process of Samsung.

“Today’s demanding mobile, high-performance computing and artificial intelligence applications require power and performance levels that push the limits of small geometries,” said Sangyun Kim, vice president of Samsung Electronics’ Foundry Design Technology team. “Our longstanding collaboration with Synopsys on EDA design flow certifications provides our joint customers with substantial advantages in power, performance and area.”

Synopsys and Samsung Foundry have continued to innovate to deliver the silicon enhancements demanded by our smart, connected world. Samsung Foundry has streamlined its 3nm process development costs and schedule, effectively evaluating its process options based on PPA design metrics. The foundry continues to include Synopsys DSO.ai technology in its workflow, using machine learning capabilities to massively expand choice exploration in chip design workflows and accelerate its process development.

“Synopsys’ strategic collaboration with Samsung Foundry has allowed us to keep pace with each generation of their process technology advancements,” said Shankar Krishnamoorthy, EDA Group General Manager, Synopsys. “By providing industry-leading EDA design flows certified on Samsung’s most advanced 3nm technology, our joint customers can maximize the capabilities of their advanced SoC designs and accelerate the path to silicon success.”